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RT9367C 1 ds9367c-01 march 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. i 2 c programmable white led driver with dual ldo general description the RT9367C is an integrated solution for backlighting and phone camera input supply. the part contains a charge pump white led driver and dual low dropout linear regulators. this ic can be shutdown by pulling ena low. in the section of charge pump, the RT9367C can power up 4 white leds with regulated constant current for uniform intensity. each channel (led1-led4) can support up to 25ma. the part maintains highest efficiency by utilizing a x1/x1.5/x2 fractional charge pump and low dropout current regulators. an internal 5-bit dac is used for brightness control. users can easily configure up to 32- step of led current by i 2 c interface. in the section of linear regulator, the RT9367C comprises a dual channel, low noise, and low dropout regulator sourcing up to 300ma at each channel. the range of output voltage can be configured from 1.1v to 3.3v by i 2 c interface. the outputs of ldo offer 3% accuracy and low dropout voltage of 250mv @300ma. the ldo also provides current limiting and output short circuit thermal folded back protection. features an integrated solution for backlighting and phone camera input supply i 2 c programmable, 32 steps dimming control and independent channel on/off control over temperature protection power on reset for data register typical 1ua low shutdown current with interface fully on charge pump white led driver ` ` ` ` ` over 93% peak efficiency over li-ion battery discharge ` ` ` ` ` typical 85% average efficiency over li-ion battery discharge ` ` ` ` ` support up to 4 white leds ` ` ` ` ` output current up to 25ma/channel 100ma total ` ` ` ` ` 60mv typical current source dropout ` ` ` ` ` 1% typical led current accuracy ` ` ` ` ` 0.7% typical led current matching ` ` ` ` ` automatic x1/x1.5/x2 charge pump mode transition ` ` ` ` ` low input noise and emi charge pump ` ` ` ` ` 5.5v over voltage protection ` ` ` ` ` power on/mode transition in-rush protection ` ` ` ` ` 1mhz random frequency oscillator ` ` ` ` ` typical 0.1ua low shutdown current dual ldo ` ` ` ` ` wide operating voltage range ` ` ` ` ` low-noise output ` ` ` ` ` no noise bypass capacitor required ` ` ` ` ` fast response in line/load transient ` ` ` ` ` low temperature coefficient ` ` ` ` ` dual ldo outputs (300ma/300ma) ` ` ` ` ` 3% max output accuracy ` ` ` ` ` current limit protection ` ` ` ` ` short circuit thermal folded back protection ` ` ` ` ` typical 0.1ua low shutdown current rohs compliant and halogen free applications camera phone, smart phone white led backlighting, cmos sensor input supply RT9367C package type qw : wqfn-20l 3x3 (w-type) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free)
RT9367C 2 ds9367c-01 march 2011 www.richtek.com pin configurations typical application circuit wqfn-20l 3x3 (top view) c2p pgnd c1n c2n nc ldo2 ldo1 avin pvin scl ena vout led1 led3 led2 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 led4 16 c1p agnd nc 10 sda marking information fm=ym dnn fm= : product code ymdnn : date code RT9367Cgqw RT9367Czqw fm ym dnn fm : product code ymdnn : date code led4 led2 led1 led3 RT9367C c fly2 16 17 18 19 vout c out 1f 20 pgnd 3, 21 (exposed pad) ldo2 14 c ldo2 1f ldo1 12 c ldo1 1f avin pvin c in1 2.2f c in2 1f v in 2.8v to 5.5v 13 6 c2p c2n 1f 2 4 c1n c1p c fly1 1f 1 5 (2k to 10k) scl sda 8 7 v cc 2.5v to 5.5v i 2 c i 2 c r2 r1 ena 9 chip enable agnd 11
RT9367C 3 ds9367c-01 march 2011 www.richtek.com timing diagram s = start condition w = write (sda = 0 ) r = read (sda = 1 ) ack = acknowledge p = stop condition start a6 a5 a4 a3 a2 a1 a0 0 i 2 c adress b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 stop sub adress data ii test mode the 1st word (chip address, r/w ) the 2nd word (sub address, data) the 3rd word (data) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 c4 c3 c2 c1 c0 start stop b7 12345678912 b6 b2 b1 b0 3456789 12 3456789 c5 c4 c3 c2 c1 c0 w s p 00 scl sda a6 a5 a4 a3 a2 a1 a0 0 a0 a1 a2 a3 a4 a5 a6 b5 00 b3 channel selection ack ack ack r/w on/off figure 1. i 2 c interface trimming diagram figure 2 s t hd,sta t su,dat t low t f t r t high t su,sto t buf ps sda scl t hd,dat v il(max) v ih(min) v il(max) v ih(min) ena
RT9367C 4 ds9367c-01 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 c1n fly capacitor 1 negative connection. 2 c2n fly capacitor 2 negative connection. 3 pgnd power ground. 4 c2p fly capacitor 2 positive connection. 5 c1p fly capacitor 1 positive connection. 6 pvin power input. 7 scl i 2 c clock input. 8 sda i 2 c data input. 9 ena chip enable (active high). 10, 15 nc no internal connection. 11 agnd analog ground. 12 ldo1 ldo 1 output. 13 avin analog power input. 14 ldo2 ldo 2 output. 16 led4 current sink for led4. 17 led3 current sink for led3. 18 led2 current sink for led2. 19 led1 current sink for led1. 20 vout charge pump output. 21 (exposed pad) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. function block diagram pvin led1 led2 led3 vout c1p led4 scl c2p c1n c2n current limitation soft start circuit dac 32 steps current setting register channel selecting register current bias uvlo bandgap reference gate driver x1/x1.5/x2 mode decision 1mhz oscillator x1/x1.5/x2 charge pump low dropout current source non-overlap driving signal v r1 32 step voltage reference register 2 r set + - avin + - 32 step voltage reference register 1 + - i 2 c otp sda ldo2 ldo1 pgnd ovp + - avin agnd ena
RT9367C 5 ds9367c-01 march 2011 www.richtek.com electrical characteristics recommended operating conditions (note 4) junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) supply input voltage, avin, pvin ---------------------------------------------------------------------------------------- ? 0.3v to 6v output voltage, vout ------------------------------------------------------------------------------------------------------ ? 0.3v to 6v other pins --------------------------------------------------------------------------------------------------------------------- - ? 0.3v to 6v power dissipation, p d @ t a = 25 c wqfn-20l 3x3 --------------------------------------------------------------------------------------------------------------- 1.471w package thermal resistance (note 2) wqfn-20l 3x3, ja ---------------------------------------------------------------------------------------------------------- 68 c/w wqfn-20l 3x3, jc --------------------------------------------------------------------------------------------------------- 7.5 c/w junction temperature -------------------------------------------------------------------------------------------------------- 150 c lead temperature (soldering, 10 sec.) ---------------------------------------------------------------------------------- 260 c esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------------------------------- 200v (v in = avin = pvin = 3.6v, c in1 = 2.2uf, c in2 = 1uf, c out = 1uf, c fly1 = c fly2 = 1uf, v f = 3.5v, i led1 = i led2 = i led3 = i led4 = 15ma, t a = 25 c, unless otherwise specification) parameter symbol conditions min typ max unit input power supply input supply voltage v in 2.8 -- 5.5 v shutdown current i shdn v in = 5v, ena = 0v -- 1 7 a charge pump led driver block under-voltage lockout threshold v in rising. 1.8 2.0 2.5 v under-voltage lockout hysteresis -- 100 -- mv quiescent of x1 mode i q_x1 -- 1 2.5 ma quiescent of x2 mode i q_x2 -- 3.5 7 ma led current i ledx accuracy i led-err i ledx = 15ma ? 8 0 +8 % current matching i ledx = 15ma ? 5 0 +5 % oscillator frequency f os c -- 1000 -- khz mode decision x1 mode to x2 mode transition voltage v ts _x2 v in falling -- 3.65 3.8 v mode transition hystersis -- 250 -- mv to be continued
RT9367C 6 ds9367c-01 march 2011 www.richtek.com (v in = avin = pvin = v ldox + 1v, c in2 = c ldo1 = c ldo2 = 1uf, t a = 25 c, unless otherwise specified.) parameter symbol conditions min typ max unit ldo block dropout voltage v drop v ldox = 3.3v, i ou t = 300ma -- 240 -- mv output voltage range v ldox 1.1 -- 3.3 v vout accuracy v i out = 1ma ? 3 -- 3 % line regulation v line v in = (v out + 0.3v) to 5.5v or v in > 2.5v, whichever is larger -- 0.01 0.2 %/v load regulation v load 1ma < i out < 300ma -- 0.01 0.6 % current limit i lim r load = 1 330 500 700 ma quiescent current i q -- 60 100 a output voltage temperature coefficent -- 100 -- ppm/ c thermal shutdown t sd -- 170 -- c thermal shutdown hysteresis t sd -- 40 -- c i 2 c block input high voltage v ih 1.5 -- 5.5 v input low voltage v il 0 -- 0.4 v clock operating frequency f scl -- -- 400 khz output low level v ol i sda = 3ma -- -- 0.4 v input high level current of scl, sda i ih -- 2 -- a bus free time between a stop and start condition t buf (note 5) 1.3 -- -- s hold time after start condition t hd,sta (note 5) 0.6 -- -- s data setup time t su,dat (note 5) 200 -- ns set-up time for stop condition t su,sto (note 5) 0.6 -- -- s input date hold time t hd,dat (note 5) 200 -- 900 ns low period of the scl clock t low (note 5) 1.3 -- -- s high period of the scl clock t high (note 5) 0.6 -- -- s clock data fall time t f (note 5) 20 -- 300 ns clock data rise time t r (note 5) 20 -- 300 ns input low time for shutdown t shdn (note 6) both scl and sda are floating 400 1000 2000 s logic-high voltage v ih 1.5 -- -- ena threshold logic-low voltage v il -- -- 0.4 v
RT9367C 7 ds9367c-01 march 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the wqfn package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. all values are referred to v ih and v il levels. note 6. in normal operation, the low time of both scl and sda must be less than 200us.
RT9367C 8 ds9367c-01 march 2011 www.richtek.com typical operating characteristics efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 input voltage (v) efficiency (%) v f = 3.1v, led = 15ma led current vs. input voltage 10 11 12 13 14 15 16 17 18 19 20 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 input voltage (v) led current (ma) v f = 3.1v, led = 15ma led1 led2 led3 led4 x1 mode quiescent current vs. input voltage 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 input voltage (v) quiescent current (ma) 15ma lde1 to 4 short x2 mode quiescent current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.83.23.6 4 4.44.85.25.6 input voltage (v) quiescent current (ma) 15ma lde1 to 4 open efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 2.6 3.1 3.6 4.1 4.6 5.1 5.6 input voltage (v) efficiency (%) v f = 3.3v, led = 25ma led current vs. input voltage 0 5 10 15 20 25 30 2.8 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) led current (ma) v f = 3.3v, led = 25ma led1 led2 led3 led4
RT9367C 9 ds9367c-01 march 2011 www.richtek.com shutdown current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.833.23.43.63.844.24.44.64.855.25.45.6 input voltage (v) shutdown current (ua) x1.5 mode inrush current response time (100 s/div) sda (5v/div) v out (1v/div) i in (200ma/div) c1p (5v/div) v in = 3.3v, v f = 3.7v, led = 15ma x2 mode inrush current response time (100 s/div) sda (5v/div) v out (1v/div) i in (200ma/div) c1p (5v/div) v in = 2.8v, v f = 3.7v, led = 15ma x2 mode inrush current response time (100 s/div) sda (5v/div) v out (1v/div) i in (200ma/div) c1p (5v/div) v in = 3v, v f = 3.7v, led = 25ma x1.5 mode inrush current response time (100 s/div) sda (5v/div) v out (1v/div) i in (200ma/div) c1p (5v/div) v in = 3.7v, v f = 3.7v, led = 25ma frequency vs. temperature 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -40-30-20-10 0 1020304050607080 temperature (c) frequency (mhz )
RT9367C 10 ds9367c-01 march 2011 www.richtek.com x1.5 mode ripple & spike time (500ns/div) c1p (5v/div) v out (100mv/div) i in (100ma/div) v in (100mv/div) v in = 3.7v, v f = 3.7v, led = 25ma x2 mode ripple & spike time (500ns/div) c1p (5v/div) v out (100mv/div) i in (100ma/div) v in (100mv/div) v in = 3v, v f = 3.7v, led = 25ma x1.5 mode ripple & spike time (500ns/div) c1p (5v/div) v out (100mv/div) i in (100ma/div) v in (100mv/div) v in = 3.3v, v f = 3.7v, led = 15ma x2 mode ripple & spike time (500ns/div) c1p (5v/div) v out (100mv/div) i in (100ma/div) v in (100mv/div) v in = 2.8v, v f = 3.7v, led = 15ma v in = 4.2v, v ldo1 = 2.6v, i ldo1 no load power on from ena time (1ms/div) v scl (5v/div) v sda (5v/div) v ldo1 (2v/div) v ena (2v/div) v in = 4.2v, v ldo1 = 2.6v, i ldo1 no load power off from ena time (1ms/div) v scl (5v/div) v sda (5v/div) v ldo1 (2v/div) v ena (2v/div)
RT9367C 11 ds9367c-01 march 2011 www.richtek.com ldo output voltage vs. load current 3.298 3.300 3.302 3.304 3.306 3.308 3.310 3.312 0 50 100 150 200 250 300 load current (ma) output voltage (v) v in = 5v ldo1 ldo2 ldo1 dropout voltage vs. load current 0 50 100 150 200 250 300 0 50 100 150 200 250 300 load current (ma) dropout voltage (mv) t = 85 c t = 25 c t = -40 c v ldo1 = 3.3v ldo2 dropout voltage vs. load current 0 50 100 150 200 250 300 0 50 100 150 200 250 300 load current (ma) dropout voltage (mv) t = 85 c t = 25 c t = -40 c v ldo2 = 3.3v ldo1 output voltage vs. i 2 c code 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 00 03 06 09 0c 0f 12 15 18 1b 1e i 2 c code output voltage (v) s t = 85 c t = 25 c t = ? 40 c ldo2 output voltage vs. i 2 c code 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 00 03 06 09 0c 0f 12 15 18 1b 1e i 2 c code output voltage (v) s t = 85 c t = 25 c t = ? 40 c ldo output voltage vs. temperature 3.275 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, i load = 1ma ldo1 ldo2
RT9367C 12 ds9367c-01 march 2011 www.richtek.com v in = 4v to 5v, v ldo1 = v ldo2 = 3.3v ldo line transient response v in (v) time (250 s/div) v ldo2 (10mv/div) 5 4 v ldo1 (10mv/div) i out1 = i out2 = 1ma i out1 = i out2 = 10ma to 50ma v in = 5v, v ldo1 = v ldo2 = 3.3v ldo load transient response i out (50ma/div) time (250 s/div) v ldo2 (20mv/div) v ldo1 (20mv/div) ldo line transient response v in (v) time (250 s/div) v ldo2 (10mv/div) 5 4 v ldo1 (10mv/div) v in = 4v to 5v, v ldo1 = v ldo2 = 3.3v i out1 = i out2 = 10ma ldo2 psrr -100 -80 -60 -40 -20 0 20 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) load = 0ma load = 1ma load = 10ma load = 100ma v ldo2 = 3.3v 0.01 0.1 1 10 100 1000 (khz) ldo1 psrr -100 -80 -60 -40 -20 0 20 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) load = 0ma load = 1ma load = 10ma load = 100ma v ldo1 = 3.3v 0.01 0.1 1 10 100 1000 (khz) i out1 = i out2 = 10ma to 150ma v in = 5v, v ldo1 = v ldo2 = 3.3v ldo load transient response i out (100ma/div) time (250 s/div) v ldo2 (50mv/div) v ldo1 (50mv/div)
RT9367C 13 ds9367c-01 march 2011 www.richtek.com applications information the RT9367C is a high efficiency charge pump white led driver. it provides 4 channels low dropout voltage current source to regulated 4 white leds current. for high efficiency, the RT9367C implements a smart mode transition for charge pump operation. the RT9367C provides i 2 c dimming function for led brightness control. input uvlo the input operating voltage range of the RT9367C is 2.8v to 5.5v. an input capacitor at the vin pin could reduce ripple voltage. it is recommended to use a ceramic 1uf or larger capacitance as the input capacitor. this ic provides an under voltage lockout (uvlo) function to prevent it from unstable issue when startup. the uvlo threshold of input rising voltage is set at 2v typically with a hysteresis 0.1v. soft start the RT9367C includes a soft start circuit to limit the inrush current at power on and mode switching. the soft start circuit limits the input current before output voltage reaching a desired voltage level. mode decision the RT9367C uses a smart mode decision method to select the working mode for maximum efficiency. the charg pump can operation at x1, x1.5 or x2 mode. the mode decision circuit senses the output voltage and led voltage for up/down selection. selecting capacitors to get better performance of RT9367C, the selection of peripherally appropriate capacitor and value is very important. these capacitors determine some parameters such as input/output ripple voltage, power efficiency and maximum supply current by charge pump. to reduce the input and output ripple effectively, the low esr ceramic capacitors are recommended. for led driver applications, the input voltage ripple is more important than output ripple. the input ripple is controlled by input capacitor c in , increasing the value of input capacitance can further reduce the ripple. practically, the input voltage ripple depends on the power supply's impedance. the flying capacitor c fly1 and c fly2 determine the supply current capability of the charge pump that will influence the overall efficiency of the system. the lower value will improve efficiency, but it will limit the led's current at low input voltage. for 4 x 25ma load over the entire input voltage range of 2.8v to 5.5v, it is recommended to use 1 f ceramic capacitor on the flying capacitor c fly1 & c fly2 . power sequence in order to assure the RT9367C's operation in normal condition, the input voltage and ena should be ready before the RT9367C get the i 2 c signal showed in figure 3 and the RT9367C can be shut down by pulling ena low. when ena is reset, the i 2 c signal also needs to be resent again for operating at normal condition. dual ldo like any low-dropout regulator, the external capacitors used with the RT9367C must be carefully selected for regulator stability and performance. using a capacitor whose value is > 1 f on the RT9367C input and the amount of capacitance can be increased without limit. the input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the ic and returned to a clean analog ground. any good quality ceramic or tantalum can be used for this capacitor. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr and line-transient response. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldos application. the RT9367C is designed specifically to work with low esr ceramic output capacitor in space-saving and performance consideration. using a ceramic capacitor whose value is at least 1 f with esr is > 20m on the RT9367C output ensures stability. the RT9367C still works well with output capacitor of other types due to the wide stable esr range. figure 4. shows the curves of allowable esr range as a function of load current for various figure 3. the power sequence scl ena sda
RT9367C 14 ds9367c-01 march 2011 www.richtek.com figure 4. stable cout esr range region of stable c out esr vs. load current 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 load current (ma) region of stable c out esr ( ? ) region of stable c out esr ( ) unstable range stable range simulation verify v in = 5v c in = c out1 = c out2 = 1uf/x7r thermal protection thermal protection limits power dissipation in RT9367C. when the operation junction temperature exceeds 170 c, the otp circuit starts the thermal shutdown function and turns the pass element off. the pass element turn on again after the junction temperature cools by 40 c. the RT9367C lowers its otp trip level from 170 c to 110 c when output short circuit occurs (ldo1 and ldo2 < 0.4v) as shown in figure 5. it limits ic case temperature under 110 c and provides maximum safety to customer while output short circuit occurring. figure 6. derating curves figure 5. short circuit thermal folded back protection when output short circuit occurs (patent) v out short to gnd 0.4v v out i out tsd otp trip point 170 c 110 c 110 c 80 c ic temperature thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT9367C, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-20l 3x3 packages, the thermal resistance ja is 68 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula: p d(max) = (125 c ? 25 c) / (68 c/w) = 1.471w for wqfn-20l 3x3 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT9367C packages, the figure 6 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn-20l 3x3 four layers pcb ( c) output capacitor values. output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. the output capacitor should be located at not more than 0.5 inch from the ldo1 and ldo2 pin of the RT9367C and returned to a clean analog ground.
RT9367C 15 ds9367c-01 march 2011 www.richtek.com i 2 c compatible interface the figure 1 shows the timing diagram of i 2 c interface. the RT9367C communicates with a host (master) using the standard i 2 c 2-wire interface. the two bus lines of scl and sda must be pulled to high when the bus is not in use. external pull-up resistors between vcc and sda/ scl pin are necessary. the recommended pull-up resistor value range is from 2k to 10k . 0 0 0 c4 c3 c2 c1 c0 0 x x x x x 0 1 0 0 b3 b2 b1 b0 32-step current setting channel selecting ? i 2 c writing cycles of ldo1 ? i 2 c writing cycles of ldo2 32-step voltage setting 0 0 1 0 0 0 0 1 0 0 0 c4 c3 c2 c1 c0 start stop 32-step voltage setting 0 0 1 0 0 1 0 1 0 0 0 c4 c3 c2 c1 c0 start stop ? i 2 c writing cycles of led driver stop start a6 a5 a4 a3 a2 a1 a0 0 a6 a5 a4 a3 a2 a1 a0 0 a6 a5 a4 a3 a2 a1 a0 0 led4 led3 led2 led1 or or on/off on/off figure 7. RT9367C i 2 c writing cycles for ldo and led driver figure 8. ldo voltage setting and led current setting figure 7 shows the writing information of dual ldo and led current. in the second word, the sub-address of dual ldo is ? 001 ? and the sub-address of led driver is ? 010 ? . for ldo, the ldo1 address is defined as ? 000 ? , ldo2 address is defined as ? 001 ? . led current vs input code 0 0.78 0f 1f 12.5 25 hex code typical ldo current (ma) ldo2 output voltage vs input code 0 1.1 0f 1f 1.8 3.3 hex code 2.5 0e typical ldo output voltage (v) ldo1 output voltage vs input code 0 1.75 0f 1f 2.5 3.3 hex code typical ldo output voltage (v) after the start condition, the i 2 c master sends a chip address. this address is seven bits long followed by an eighth bit which is a data direction bit (r/w). the RT9367C address is 1010100 (54h) and is a receive-only (slave) device. the second word selects the register to which the data will be written. the third word contains data to write to the selected register. the data of second byte (b0 to b3), a ? 0 ? indicates a disable and a ? 1 ? indicates an enable function. the data of third byte (c0 to c4) indicates a 32-steps setting of ldo1, ldo2 output voltage or the led current of backlight.
RT9367C 16 ds9367c-01 march 2011 www.richtek.com figure 8. illustrates the dual ldos' output voltage and led current setting information. the output voltage of ldo1 could be divided to 32-step levels between 1.75v (hex code = 0) and 3.3v (hex code = 1f). and the output voltage of ldo2 is separated to two regions, one is from 1.1v (hex code = 0) to 1.8v (hex code = 0e) and the other is from 2.5v (hex code = 0f) to 3.3v (hex code = 1f). in addition, the led current could be divided to 32- step levels between 0.8ma (hex code = 0) and 25ma (hex code = 1f). voltage (v) voltage (v) voltage (v) voltage (v) code c4~c0 ldo1 ldo2 code c4~c0 ldo1 ldo2 code c4~c0 ldo1 ldo2 code c4~c0 ldo1 ldo2 00000 1.75 1.10 01000 2.15 1.50 10000 2.55 2.55 11000 2.95 2.95 00001 1.80 1.15 01001 2.20 1.55 10001 2.60 2.60 11001 3.00 3.00 00010 1.85 1.20 01010 2.25 1.60 10010 2.65 2.65 11010 3.05 3.05 00011 1.90 1.25 01011 2.30 1.65 10011 2.70 2.70 11011 3.10 3.10 00100 1.95 1.30 01100 2.35 1.70 10100 2.75 2.75 11100 3.15 3.15 00101 2.00 1.35 01101 2.40 1.75 10101 2.80 2.80 11101 3.20 3.20 00110 2.05 1.40 01110 2.45 1.80 10110 2.85 2.85 11110 3.25 3.25 00111 2.10 1.45 01111 2.50 2.50 10111 2.90 2.90 11111 3.30 3.30 code c4~c0 led current (ma) code c4~c0 led current (ma) code c4~c0 led current (ma) code c4~c0 led current (ma) 00000 0.8 01000 7.0 10000 13.3 11000 19.5 00001 1.6 01001 7.8 10001 14.0 11001 20.3 00010 2.3 01010 8.6 10010 14.8 11010 21.1 00011 3.1 01011 9.4 10011 15.6 11011 21.8 00100 3.9 01100 10.1 10100 16.4 11100 22..6 00101 4.7 01101 10.9 10101 17.2 11101 23.4 00110 5.5 01110 11.7 10110 17.9 11110 24.2 00111 6.2 01111 12.5 10111 18.7 11111 25.0 table 1. ldo voltage setting table 2. ldo current setting layout consideration the RT9367C is a high-frequency switched-capacitor converter. careful pcb layout is necessary. for best performance, place all peripheral components as close to the ic as possible. place c in1 , c in2 , c out , c ldo1 , c ldo2 , c fly1 , and c fly2 near to avin, pvin, vout, ldo1, ldo2, c1p, c1n, c2p, c2n, and gnd pin respectively. a short connection is highly recommended. the following guidelines should be strictly followed when designing a pcb layout for the RT9367C. ` the exposed gnd pad must be soldered to a large ground plane for heat sinking and noise prevention. the throughhole vias located at the exposed pad is connected to ground plane of internal layer. ` vin traces should be wide enough to minimize inductance and handle the high currents. the trace running from battery to chip should be placed carefully and shielded strictly. ` input and output capacitors must be placed close to the part. the connection between pins and capacitor pads should be copper traces without any through-hole via connection.
RT9367C 17 ds9367c-01 march 2011 www.richtek.com figure 9. pcb layout guide battery gnd plane gnd plane c out c fly2 c fly1 c in1 c in2 c ldo2 c ldo1 output capacitor must be placed between gnd and vout to reduce noise coupling from charge pump to leds. the traces running from pins to flying capacitor should be short and wide to reduce parasitic resistance and prevent noise radiation. the exposed pad, gnd pad should be connected to a strong ground plane for heat sinking and noise prevention. all the traces of led and vin running from chip to lcm module should be shielded and isolated by ground plane. c2p pgnd c1n c2n nc ldo2 ldo1 avin pvin scl ena vout led1 led3 led2 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 led4 16 c1p agnd nc 10 sda gnd plane ` the flying capacitors must be placed close to the part. the traces running from the pins to the capacitor pads should be as wide as possible. long traces will also produce large noise radiation caused by the large dv/dt on these pins. short trace is recommended. ` all the traces of led and vin running from pins to lcm module should be shielded and isolated by ground plane. the shielding prevents the interference of high frequency noise coupled from the charge pump. ` output capacitor must be placed between vng and vout to reduce noise coupling from charge pump to leds.
RT9367C 18 ds9367c-01 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension d imensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.900 3.100 0.114 0.122 d2 1.650 1.750 0.065 0.069 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 20l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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